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Unmodified compressed instruction support
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Toby Jaffey
parent
3d83844d5c
commit
652094c289
1 changed files with 240 additions and 0 deletions
240
uvm32/rv32c.h
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240
uvm32/rv32c.h
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// https://riscv.github.io/riscv-isa-manual/snapshot/unprivileged/#_compressed_instruction_formats about 1/3 the way
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// down. https://www.cs.sfu.ca/~ashriram/Courses/CS295/assets/notebooks/RISCV/RISCV_CARD.pdf
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// This adds -C extension support to mini-rv32ima.
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#define MINIRV32_HANDLE_OTHER_OPCODE \
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default: \
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{ \
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int cimm = ((((ir >> 2) & 0x1f)) | (((ir >> 12) & 1) << 5)); \
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uint32_t cimmext = (cimm & 0x20) ? (cimm | 0xffffffc0) : cimm; \
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switch (ir & 3) \
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{ \
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case 0b00: \
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{ \
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ir &= 0xffff; \
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pc -= 2; \
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uint32_t uimm = (((ir >> 5) & 1) << 6) | (((ir >> 6) & 1) << 2) | (((ir >> 10) & 7) << 3); \
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switch (ir >> 13) \
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{ \
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case 0b000: /*c.addi4spn ADD Imm * 4 + SP (I think this is right? Maybe)?*/ \
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cimm = (((ir >> 5) & 1) << 3) | (((ir >> 6) & 1) << 2) | (((ir >> 7) & 0xf) << 6) \
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| (((ir >> 11) & 3) << 4); \
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cimmext = (cimm & 0x200) ? (cimm | 0xfffffc00) : cimm; \
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rdid = ((ir >> 2) & 7) + 8; \
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/*printf( "c.addi4spn %08x %d / %d @ %08x\n", REG( 2 ), cimmext, rdid, debugpc );*/ \
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rval = REG(2) + cimmext; \
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break; \
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case 0b010: /*c.lw*/ \
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/*printf( "L %08x -> %08x/%08x\n", pc, REG(((ir>>7)&7)+8), uimm );*/ \
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rval = MINIRV32_LOAD4(REG(((ir >> 7) & 7) + 8) + uimm); \
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rdid = ((ir >> 2) & 7) + 8; \
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break; \
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case 0b110: /*c.sw*/ \
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/*printf( "S %08x -> %08x/%08x\n", pc, REG(((ir>>7)&7)+8), uimm );*/ \
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MINIRV32_STORE4(REG(((ir >> 7) & 7) + 8) + uimm, REG(((ir >> 2) & 7) + 8)); \
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rdid = 0; \
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break; \
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default: \
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/* printf( "Unknown Opcode at %08x\n", debugpc ); */ \
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trap = (2 + 1); \
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break; \
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} \
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break; \
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} \
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case 0b01: \
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ir &= 0xffff; \
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pc -= 2; \
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switch (ir >> 13) \
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{ \
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case 0b000: /*c.addi*/ \
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rval = REG(rdid) + cimmext; \
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break; \
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case 0b010: /*c.li*/ \
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rval = cimmext; \
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break; \
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case 0b011: /*c.lui / ADDI16SP*/ \
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switch (((ir >> 7) & 0x1f)) \
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{ \
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case 0: \
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break; \
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case 2: /*c.addi16sp TODO: Check me.*/ \
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{ \
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cimm = (((ir >> 12) & 1) << 9) | (((ir >> 2) & 1) << 5) | (((ir >> 5) & 1) << 6) \
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| (((ir >> 6) & 1) << 4) | (((ir >> 3) & 3) << 7); \
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cimmext = (cimm & 0x200) ? (cimm | 0xfffffc00) : cimm; \
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/*printf( "c.addi16sp -> %08x -> %08x\n", REG(2), cimmext );*/ \
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rval = REG(2) + cimmext; \
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break; \
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} \
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default: /*c.lui*/ \
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rval = cimm << 12; \
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break; \
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}; \
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break; \
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case 0b100: /* MISC-ALU */ \
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rdid = (rdid & 7) + 8; \
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switch ((ir >> 10) & 3) \
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{ \
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case 0: /*c.srli*/ \
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rval = REG(rdid) >> cimm; \
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break; \
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case 1: /*c.srai*/ \
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rval = ((int32_t)REG(rdid)) >> cimm; \
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break; \
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case 2: /*c.andi*/ \
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rval = REG(rdid) & cimm; \
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break; \
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case 3: /*c.other*/ \
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{ \
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uint32_t rs2 = REG((cimm & 7) + 8); \
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switch (cimm >> 3) \
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{ \
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case 0: /* c.sub */ \
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rval = REG(rdid) - (rs2); \
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break; \
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case 1: /* c.xor */ \
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rval = REG(rdid) ^ (rs2); \
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break; \
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case 2: /* c.or */ \
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rval = REG(rdid) | (rs2); \
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break; \
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case 3: /* c.and */ \
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rval = REG(rdid) & (rs2); \
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break; \
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default: /* res */ \
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/* printf( "Unknown Opcode at %08x\n", debugpc ); */ \
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trap = (2 + 1); \
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break; \
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} \
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} \
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} \
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break; \
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case 0b001: /*c.jal + NOTE: Is c.addiw on RV64*/ \
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case 0b101: /*c.j*/ \
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{ \
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uint32_t limm = (((ir >> 2) & 0x1) << 5) | (((ir >> 3) & 0x7) << 1) | (((ir >> 6) & 0x1) << 7) \
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| (((ir >> 7) & 0x1) << 6) | (((ir >> 8) & 0x1) << 10) \
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| (((ir >> 9) & 0x3) << 8) | (((ir >> 11) & 0x1) << 4) \
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| (((ir >> 12) & 1) << 11); \
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if (limm & 0x800) \
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limm |= 0xfffff000; \
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if ((ir >> 13) == 0b001) \
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{ \
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rdid = 1; \
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rval = pc + 4; \
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/*printf( "jal r1 = %08x\n", rval );*/ \
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} \
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else \
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rdid = 0; \
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pc = pc + limm - 2; \
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} \
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break; \
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case 0b110: /*c.beqz*/ \
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case 0b111: /*c.bnez*/ \
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{ \
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rdid = 0; \
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uint32_t limm = (((ir >> 2) & 0x1) << 5) | (((ir >> 3) & 0x3) << 1) \
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| (((ir >> 10) & 0x3) << 3) | (((ir >> 5) & 0x3) << 6) \
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| (((ir >> 12) & 0x1) << 8); \
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if (limm & 0x100) \
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limm |= 0xffffff00; \
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if ((ir >> 13) == 0b110) \
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{ \
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if (REG(((ir >> 7) & 0x7) + 8) == 0) \
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{ \
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pc = pc + limm - 2; \
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} \
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} \
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else \
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{ \
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if (REG(((ir >> 7) & 0x7) + 8) != 0) \
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{ \
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pc = pc + limm - 2; \
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} \
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} \
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break; \
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} \
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default: \
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/* printf( "Unknown Opcode at %08x\n", debugpc ); */ \
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trap = (2 + 1); \
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break; \
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} \
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break; \
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case 0b10: \
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ir &= 0xffff; \
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pc -= 2; \
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switch (ir >> 13) \
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{ \
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case 0b000: /*c.slli*/ \
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rval = REG(rdid) << cimm; \
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break; \
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case 0b100: /*c.mv / c.add / c.jr (/c.ret) / c.jalr */ \
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if ((ir >> 12) & 1) \
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{ \
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if ((((ir >> 2) & 0x1f) != 0) && rdid != 0) \
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{ \
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/*printf( "Adding r %d / %d\n", (ir>>2)&0x1f, rdid );*/ \
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rval = REG((ir >> 2) & 0x1f) + REG(rdid); /* c.add */ \
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} \
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else if (rdid != 0) \
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{ \
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rval = pc + 4; \
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pc = REG(rdid) - 4; /*c.jr*/ \
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rdid = 1; /* c.jalr */ \
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} \
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else \
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{ \
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/* printf( "Unknown Opcode at %08x\n", debugpc ); */ \
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trap = (3 + 1); \
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break; /* EBREAK 3 = "Breakpoint" */ \
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} \
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} \
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else \
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{ \
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if ((((ir >> 2) & 0x1f) != 0) && rdid != 0) \
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{ \
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/* c.mv */ \
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rval = REG((ir >> 2) & 0x1f); \
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/* printf( "c.mv %d %d -> %08x @ %08x\n", rdid, (ir >> 2) & 0x1f, rval,pc); */ \
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} \
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else if (rdid != 0) \
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{ \
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pc = REG(rdid) - 4; \
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rdid = 0; /* c.jr */ \
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} \
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else \
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{ \
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/* illegal opcode */ \
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/* printf( "Unknown Opcode at %08x\n", debugpc ); */ \
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trap = (2 + 1); \
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break; \
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} \
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} \
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break; \
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case 0b110: /*c.swsp / c.sw(SP)*/ \
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rdid = 0; \
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/*printf( "C.SWSP gp=%08x -> REG(2)=%08x + %08x <<< %08x\n", REG(3), REG(2), (((ir>>7)&3)<<6) \
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* + (((ir>>9)&0xf)<<2), REG(((ir>>2)&0x1f)) ); */ \
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MINIRV32_STORE4(REG(2) + (((ir >> 7) & 3) << 6) + (((ir >> 9) & 0xf) << 2), \
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REG(((ir >> 2) & 0x1f))); \
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break; \
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case 0b010: /*c.lwsp / c.lw(SP)*/ \
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/*printf( "C.LWSP gp=%08x -> REG(2)=%08x + %08x <<< %08x\n", REG(3), REG(2), (((ir>>2)&3)<<6) \
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* + (((ir>>4)&0x7)<<2) + (((ir>>12)&1)<<5), REG(((ir>>2)&0x1f)) );*/ \
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rval = MINIRV32_LOAD4(REG(2) + (((ir >> 2) & 3) << 6) + (((ir >> 4) & 0x7) << 2) \
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+ (((ir >> 12) & 1) << 5)); \
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rdid = ((ir >> 7) & 0x1f); \
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break; \
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default: \
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/* printf( "Unknown Opcode at %08x\n", debugpc ); */ \
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trap = (2 + 1); \
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break; \
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} \
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break; \
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default: \
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/* printf( "Unknown Opcode at %08x\n", debugpc ); */ \
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trap = (2 + 1); \
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break; \
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} \
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}
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